In computer systems, communication between the central processing unit (CPU) and electronic devices external to the CPU is accomplished by an interconnecting bus. A bus is a parallel set of conductors comprising lines dedicated to specific purposes, such as bits for addresses and data, and for control signals to manage communication. The number of parallel lines in a bus can vary. Some protocols have 16 address bits and 16 data bits, for example, and other protocols may have 32 of each. In some protocols the same set of parallel conductors are multiplexed between data and addresses. Control signals may also vary.
In bus communication, the purpose is to transfer data words from one location to another. The data is expressed on the data lines, and the locations are expressed by addresses on the address lines. The control lines carry signals such as interrupt requests, read/write commands, and the like, for facilitating and directing the communication. The order and speed of communication is controlled by high-speed oscillators (clocks), which pace the addressing and transfer of data.
Early computer clocks ran at, for example, eight megahertz, and, at least theoretically, a specific digital operation may be performed each cycle. At eight megahertz, a cycle is 125 nanoseconds. Computers at the time of this application commonly operate at 66 megahertz. Models entering the market at this time operate at more than 100 megahertz.
In early personal computer designs, the bus, the CPU, and all devices connected to the bus ran at the same speed, which enabled accessories, such as additional memory, to be directly plugged into the system bus. In state-of-the-art computers, CPUs have become significantly faster than some other devices, which requires buses to run at different speeds for efficient utilization of the CPU and operation of peripheral devices.
One solution to difficulties created by increasing speed of CPUs is a bus provided by Intel Corporation called the Peripheral Component Interconnect (PCI) Bus which permits the CPU and memory to run on one bus at one speed while slower input/output devices may operate at a slower speed on another bus. With the CPU isolated from the system bus, PC manufacturers can design motherboards to work with several generations of PCs without having to redesign the motherboard's I/O subsystem for each new processor.
Although the PCI bus is an improvement over previous bus designs, today's ever-evolving CPUs are revealing limitations of the PCI bus structure. For example, greatly increased switching speeds of the signals require that signals may need to be switched at a lower voltage than the 3.3 volt transitions in the PCI design, such as 1.5 volts.
One bus structure that has been developed to work with very fast buses is called the Gunning Transceiver Logic (GTL) bus structure, and will be referred to in descriptions below.
An important criteria for proper operation of bus structures in general is that the bus be terminated properly. By termination is meant the manner in which the lines of the bus are connected to devices that supply electrical current to the bus at the voltage at which the devices on the bus are designed to operate. Such devices are referred to by those with skill in the art by various names, and the variety of terms used can be confusing. In general, however, these devices supply current to lines in a bus structure at a relatively fixed and regulated voltage, and may also supply electrical power to other devices and components than the bus with which the present invention is concerned. For the purposes of this application these electrical supplies will be called voltage-regulated current sources, and sometimes just current sources.
Proper termination becomes especially important in high performance bus structures such as the new GTL structure. Proper and workable termination is to ensure that voltage difference between the ends of the bus be maintained within some specified range such as 50 millivolts, for example. Improper termination leading to excessive drift in bus voltage may cause generation of large currents within the bus structure which may damage delicate integrated circuit chips that are connected, and other vulnerable structures as well, such as the bus lines themselves. Further, improper termination may result in irregular reflection patterns on the bus which may lower the efficiency of smoothing out signal transitions by gunning transceivers in a GTL structure. It is well known in the art that proper voltage termination of busses is of foremost concern.
One technique known to the present inventor to be used to try to maintain relatively constant bus voltage is implementation of multiple regulated current sources to the bus structure. This requires ability for each source to independently compensate in case of voltage drift using cross regulation feedback. Such a system is illustrated in FIG. 1.
FIG. 1 is a simplified block diagram showing termination of a bus structure using multiple sources. Bus 102, shown as a single line in the figure, represents a multi-conductor bus, which has pull-up resistors 104 and 106 connected at each end of the bus. There are actually separate resistors for separate lines in the bus, but the single line analogy of the figure avoids complexity and provides a clearer indication of the function of the various elements.
Two integrated circuit chips 103 are shown connected to bus 102. These chips represent any of several devices that might be connected to the bus, such as a CPU and the like. Voltage regulated sources 108 and 110 are connected to the bus via pull-up resistors 106 and 108, to maintain voltage magnitude and stability at both ends of bus 102. Feedback lines 112 and 113 connecting sources 108 and 110 provide feedback information between the sources so the system can compensate for drift of either source. In this way, the voltage difference between the two ends of the bus is meant to be maintained within in a specified range.
In this relatively complicated arrangement, using multiple voltage regulated sources at different points in a bus structure, accurate and uniform voltage regulation throughout the bus is difficult to achieve because the feedback signals have discernible lag times. Oscillations are known to result from the delayed feedback, and such oscillations may actually be self reinforcing.
Another problem with the multiple source solution is that all the extra components increases the cost of the overall structure. What is needed is a simplified, reliable, and relatively low-cost voltage termination apparatus and method for high performance bus structures.